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_______________general description the MAX100 ecl-compatible, 250msps, 8-bit analog-to- digital converter (adc) allows accurate digitizing of ana- log signals from dc to 125mhz (nyquist frequency). designed with maxim? proprietary advanced bipolar processes, the MAX100 contains a high-performance track/hold (t/h) amplifier and a quantizer in a single ceramic strip-line package. the innovative design of the internal t/h assures an exceptionally wide input bandwidth of 1.2ghz and aper- ture delay uncertainty of less than 2ps, resulting in a high 6.8 effective bits performance. special comparator output design and decoding circuitry reduce out-of-sequence code errors. the probability of erroneous codes occurring due to metastable states is reduced to less than 1 error per 10 15 clock cycles. unlike other adcs, which can have errors that result in false full-scale or zero-scale out- puts, the MAX100 keeps the magnitude to less than 1lsb. the analog input is designed for either differential or single- ended use with a ?70mv range. sense pins for the refer- ence input allow full-scale calibration of the input range or facilitate ratiometric use. midpoint tap for the reference string is available for applications that need to modify the output coding for a user-defined bilinear response. use of separate high-current and low-current ground pins pro- vides better noise immunity and highest device accuracy. dual output data paths provide several data output modes for easy interfacing. these modes can be configured as either one or two identical latched ecl outputs. an 8:16 demultiplexer mode that reduces the output data rates to one-half the clock rate is also available. for applications that require faster data rates, refer to maxim? max101, which allows conversion rates up to 500msps. ____________________________features ? 250msps conversion rate ? 6.8 effective bits at 125mhz ? less than ?/2lsb inl ? 50 differential or single-ended inputs ? ?70mv input signal range ? reference sense inputs ? ratiometric reference inputs ? configurable dual-output data paths ? latched, ecl-compatible outputs ? low error rate, less than 10 -15 metastable states ? selectable on-chip 8:16 demultiplexer ? 84-pin ceramic flat pack ________________________applications high-speed digital instrumentation high-speed signal processing medical systems radar/sonar high-energy physics communications ______________ordering information MAX100 ________________________________________________________________ maxim integrated products 1 dclk dclk a=b div mod bdata (b0?7) adata (a0?7) ain+ ain- clk clk va rt va rts va rb va rbs va ct va cts l a t c h e s b u f f e r l a t c h e s mode control track/ hold flash converter 8 8 8 _________________________________________________________functional diagram call toll free 1-800-998-8800 for free literature. part MAX100cfr* 0? to +70? temp. range pin-package 84 ceramic flat pack (with heatsink) 19-0282; rev 0; 7/94 evaluation kit available *contact factory for 84-pin ceramic flat pack without heatsink. 250msps, 8-bit adc with track/hold
MAX100 250msps, 8-bit adc with track/hold 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) electrical characteristics (v ee = -5.2v, v cc = +5v, r l = 50 to -2v, va rt = 1.02v, va rb = -1.02v, t min to t max = 0? to +70?, t a = +25?, unless otherwise noted.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: the digital control inputs are diode protected; however, permanent damage may occur on unconnected units under high- energy electrostatic fields. keep unused units in conductive foam or shunt the terminals together. discharge the conduc- tive foam to the destination socket before insertion. note 2: typical thermal resistance, junction-to-case r q jc = 5?/w and thermal resistance, junction to ambient (MAX100ca) r q ja = 12?/w, providing 200 lineal ft/min airflow with heatsink. see package information. supply voltages v cc .............................................................................0v to +7v v ee ...............................................................................-7v to 0v v cc - v ee ............................................................................+12v analog input voltage .............................................................?v digital input voltage .................................................-2.3v to +0v reference voltage (va rt ) .....................................-0.3v to +1.5v reference voltage (va rb ).....................................-1.5v to +0.3v data output current ..........................................................-33ma dclk output current ........................................................-43ma operating temperature range...............................0? to +70? operating junction temperature (note 2)............0? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+250? adata, bdata conditions ?.5 bits 8 resolution lsb ?.6 inl integral nonlinearity (note 4) units min typ max symbol parameter f clk = 250mhz, v in = 95% full scale (note 5) bits 7.1 7.4 6.8 enob effective bits figure 5 figure 5 (note 7) f ain = 50mhz, f clk = 250mhz, v in = 95% full scale (note 6) ps 2 t aj ps 270 t aw aperture width aperture jitter 230 315 msps 250 f clk maximum conversion rate db 44.5 snr signal-to-noise ratio ghz 1.2 bw 3db analog input bandwidth ain+ to ain-, table 2, t a = t min to t max mv -305 -215 v in input voltage range ain+ and ain- with respect to gnd t a = t min to t max ain+, ain-, t a = t min to t max /? 0.008 input resistance temperature coefficient 49 51 r i input resistance mv 1.8 2.5 lsb mv -17 +32 v io input offset voltage least-significant-bit size t a = +25? t a = t min to t max adata, bdata, no missing codes ?.75 t a = +25? t a = t min to t max lsb ?.85 dnl differential nonlinearity f ain = 10mhz f ain = 50mhz f ain = 125mhz full scale zero scale accuracy dynamic specifications analog input
MAX100 250msps, 8-bit adc with track/hold _______________________________________________________________________________________ 3 electrical characteristics (continued) (v ee = -5.2v, v cc = +5v, r l = 50 to -2v, va rt = 1.02v, va rb = -1.02v, t min to t max = 0? to +70?, t a = +25?, unless otherwise noted.) (note 3) va rt to va rb -5 20 -1.95 -1.60 conditions v cc = 5.0v adata, bdata, dclk, dclk ma 710 i cc positive supply current v -1.95 -1.50 v ol digital output low voltage 464 670 116 175 r ref reference string resistance /? 0.02 reference string resistance temperature coefficient units min typ max symbol parameter div, mod, a=b, clk, clk , t a = t min to t max v -1.5 v il digital input low voltage (note 8) div, mod, a=b, clk, clk , t a = t min to t max v -1.07 v ih digital input high voltage (note 8) div, mod, a=b = -1.8v, t a = t min to t max ? 080 i il clk, clk , v il = -1.8v (no termination), t a = t min to t max digital input low current -5 20 div, mod, a=b = -0.8v, t a = t min to t max ? 080 i ih clk, clk , v ih = -0.8v (no termination), t a = t min to t max digital input high current t a = +25? t a = t min to t max -1.02 -0.70 t a = +25? t a = t min to t max adata, bdata, dclk, dclk v -1.10 -0.70 v oh digital output high voltage t a = +25? t a = t min to t max v ee = -5.2v t a = +25? ma -780 i ee negative supply current t a = t min to t max -750 -560 v incm = ?.5v t a = t min to t max db cmrr common-mode rejection ratio 35 db 40 v cc (nom) = ?.25v power-supply rejection ratio psrr t a = t min to t max reference input logic inputs logic outputs (note 9) power requirements v ee (nom) = ?.25v 40
output code integral nonlinearity vs. output code 0.75 0.50 0.25 0 -0.25 0 64 128 192 256 -0.50 -0.75 inl (lsbs) output code differential nonlinearity vs. output code 0.75 0.50 0.25 0 -0.25 0 dnl (lsbs) 64 128 192 256 -0.50 -0.75 __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) MAX100 250msps, 8-bit adc with track/hold 4 _______________________________________________________________________________________ timing characteristics (v ee = -5.2v, v cc = +5v, r l = 50 to -2v, va rt = 1.02v, va rb = -1.02v, t a = +25?, unless otherwise noted.) div = 0, figure 1 div = 1, figure 2 clk, clk , figures 1 and 2 0.8 2.4 clk, clk , figures 1 and 2 ns 1.9 5.7 t pd1 clk to dclk propagation delay conditions see figures 3 and 4 and table 1 (delay depends on output mode) 20% to 80% clock cycles 8 1/2 8 1/2 t npd 7 1/2 7 1/2 pipeline delay (latency) 7 1/2 7 1/2 ps 700 t r 500 rise time ns 1.9 t pwh ns 1.9 5.0 t pwl clock pulse width low clock pulse width high units min typ max symbol parameter div = 0, figure 1 div = 1, figure 2 0.5 2.2 ns -1.4 -0.1 t pd2 dclk to a/bdata propagation delay dclk data dclk data 20% to 80% ps 550 t f 600 fall time divide-by-1 mode divide-by- 2 mode bdata adata note 3: all devices are 100% production tested at +25? and are guaranteed by design for t a = t min to t max as specified. note 4: deviation from best-fit straight line. see integral nonlinearity section. note 5: see the signal-to-noise ratio and effective bits section in the definitions of specifications. note 6: snr calculated from effective bits performance using the following equation: snr (db) = 1.76 + (6.02) (effective bits). note 7: clock pulse width minimum requirements t pwl and t pwh must be observed to achieve stated performance. note 8: functionality guaranteed for -1.07 v ih -0.7 and -2.0 v il -1.5. note 9: outputs terminated through 50 to -2.0v.
MAX100 250msps, 8-bit adc with track/hold _______________________________________________________________________________________ 5 f clk = 250mhz, f ain = 120.4462mhz ser = -42.3db, noise floor = -65.4db frequency (mhz) fft plot (f ain = 120.4462mhz) 0 -10 -20 -30 -40 signal amplitude (db) -50 -60 -70 -80 -90 -100 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 f clk = 250mhz, f ain = 10.4462mhz ser = -45.87db, noise floor = -68.5db fft plot (f ain = 10.4462mhz) -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 12.5 25 37.5 50 62.5 0 signal amplitude (db) frequency (mhz) 0 050 effective bits vs. analog input frequency MAX100-10 f ain (mhz) effective bits 100 150 200 250 300 1 2 3 4 5 6 7 8 f clk = 250mhz, v in = 95% fs 050 100 150 200 250 0 MAX100-12 f ain (mhz) effective bits 1 2 3 4 5 6 7 8 effective bits vs. analog input frequency t case = +80?, f clk = 250mhz, v in = 95% fs 300 50 100 150 200 250 0 0 effective bits vs. clock frequency MAX100-11 f clk (mhz) effective bits 1 2 3 4 5 6 7 8 f ain = 10.4mhz, v in = 95% fs 050 100 150 200 250 0 MAX100-13 f ain (mhz) effective bits 1 2 3 4 5 6 7 8 t case = -15?, f clk = 250mhz v in = 95% fs effective bits vs. analog input frequency ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
MAX100 250msps, 8-bit adc with track/hold 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) a = clk, 200mv/div b = dclk, 200mv/div a b clock relationship (divide-by-1 mode) timebase = 1ns/div, f clk = 250mhz a = clk, 500mv/div b = dclk, 500mv/div c = adata, 500mv/div a b c clock/data (divide-by-1 mode) timebase = 2ns/div, f clk = 250mhz a = clk, 500mv/div b = dclk, 500mv/div c = adata, 500mv/div clock/data (divide-by-2 mode) a b c timebase = 2ns/div, f clk = 250mhz timebase = 1ns/div, t f = 596ps data output (negative edge) 100mv/div adata output a = dclk, 200mv/div b = adata, 200mv/div clock/data detail (divide-by-5 mode) timebase = 5ns/div, f clk = 250mhz a b timebase = 1ns/div, t r = 580ps digital clock (positive edge) dclk 100mv/div
MAX100 250msps, 8-bit adc with track/hold _______________________________________________________________________________________ 7 ______________________________________________________________pin description 12 mod modulus. mod and div select the output modes. see table 1. 5, 6, 9, 10, 31, 33, 35, 48, 58, 59, 63, 81, 83 n.c. no connect?here is no internal connection to these pins. 8, 21, 43, 56 vcc positive power supply, +5v ?% nominal 13 dclk complementary differential clock outputs. used to synchronize following circuitry: adata and bdata outputs are valid t pd2 after the rising edge of dclk. see figures 1?. 16 a=b sets adata equal to bdata when asserted (a=b = 1). see table 1. 11 div divide enable input. div and mod select the output modes. see table 1. 3, 61 clk complementary differential clock inputs. can be driven from standard 10k ecl with the following considerations: internally, pins 2 & 62 and 3 & 61 are the ends of a 50 transmission line. either end can be driven, with the other end terminated with 50 to -2v. see typical operating circuit. 4, 7, 15, 49, 57, 60, 64, 67, 70, 71, 74, 77, 78, 79, 82, 84 gnd power-supply ground. connect gnd and dgnd pins (note 10). 2, 62 clk name function 1 pad internal connection, leave open. pin 17, 20, 23, 26, 36, 39, 42, 45 a7?0 19, 22, 25, 28, 38, 41, 44, 47 b7?0 adata and bdata outputs. a0 and b0 are the lsbs, and a7 and b7 are the msbs. adata and bdata outputs conform to standard 10k ecl logic swings and drive 50 transmission lines. terminate with 50 to -2v. see figures 1?. 18, 24, 27, 30, 34, 37, 40, 46 dgnd power-supply ground. connect all ground (gnd, dgnd) pins together, as described in note 10. 29 sub circuit substrate contact. this pin must be connected to vee. 32, 69, 80 vee negative power supply, -5.2v ?% nominal 50 va rt positive reference voltage input (note 11) 51 va rts positive reference voltage sense (note 11) 14 dclk
MAX100 250msps, 8-bit adc with track/hold 8 _______________________________________________________________________________________ _________________________________________________pin description (continued) 72, 73 ain+ 75, 76 ain- analog inputs, internally terminated with 50 to ground. full-scale linear input range is approximately ?70mv. drive ain+ and ain- differentially for best high-frequency performance. 54 va rbs negative reference voltage sense (note 11) 55 va rb negative reference voltage input (note 11) 65 tp3 internal node. do not connect. 66 tp2 internal node. do not connect. 68 tp1 internal connection. this pin must be connected to gnd. 52 va cts reference bias resistor center-tap sense (note 12) 53 va ct reference bias resistor center tap (note 12) name function pin note 10: use a multilayer board with a separate layer dedicated to ground. connect gnd and dgnd in separate areas in the ground plane (separated by at least 1/4 inch) and at only one location on the board (see typical operating circuit ). note 11: reference bias supply. use a separate high-quality supply for these pins. carefully bypassing these pins to achieve noise-free operation of the reference supplies contributes directly to high adc accuracy. note 12: the center-tap connection of the MAX100 is normally left open. it can be driven with a bias voltage, but should be bypassed carefully (refer to note 11). clk adata bdata clk dclk dclk t pd1 t pd2 t pwh t pwl figure 1. output timing: divide-by-1 mode (div = 0)
MAX100 250msps, 8-bit adc with track/hold _______________________________________________________________________________________ 9 clk adata bdata clk dclk dclk t pd1 t pd2 t pwh t pwl figure 2. output timing: divide-by-2 or divide-by-5 mode (div = 1) adata bdata clk dclk t pd1 t pd2 t npd 12345678 n - 1 n n + 1 n - 1 n n + 1 n - 1 n n + 1 figure 3. output timing: clock to data, divide-by-1 mode (fast mode, div = 0) adata bdata clk dclk t pd2 t npd n - 1 n + 3 n - 2 n n + 2 n - 1 n n + 1 n + 2 n - 2 1234 5 n + 1 figure 4. output timing: divide-by-2 mode (div = 1)
MAX100 250msps, 8-bit adc with track/hold 10 ______________________________________________________________________________________ ______definitions of specifications signal-to-noise ratio and effective bits signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other analog-to-digital (a/d) output signals. the theoretical minimum a/d noise is caused by quantization error and is a direct result of the adc? reso- lution: snr = (6.02n + 1.76)db, where n is the number of effective bits of resolution. therefore, a perfect 8-bit adc can do no better than 50db. the fft plots in the typical operating characteristics show the output level in various spectral bands. effective bits is calculated from a digital record taken from the adc under test. the quantization error of the ideal converter equals the total error of the device. in addition to ideal quantization error, other sources of error include all dc and ac nonlinearities, clock and aperture jitter, missing output codes, and noise. noise on references and supplies also degrades effective bits performance. the adc? input is a sine wave filtered with an anti-alias- ing filter to remove any harmonic content. the digital record taken from this signal is compared against a mathematically generated sine wave. dc offsets, phase, and amplitudes of the mathematical model are adjusted until a best-fit sine wave is found. after subtracting this sine wave from the digital record, the residual error remains. the rms value of the error is applied in the fol- lowing equation to yield the adc? effective bits. measured rms error effective bits = n - log 2 ( ? ) ideal rms error where n is the resolution of the converter. in this case, n = 8. the worst-case error for any device will be at the con- verter? maximum clock rate with the analog input near the nyquist rate (1/2 the input clock rate). aperture width and jitter aperture width is the time the t/h circuit takes to dis- connect the hold capacitor from the input circuit (i.e., to turn off the sampling bridge and put the t/h in hold mode). aperture jitter is the sample-to-sample variation in aperture delay (figure 5). error rates errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. the resulting output code for many typical converters can be incorrect, including false full- or zero-scale output. the MAX100? unique design reduces the magnitude of this type of error to 1lsb, and reduces the probability of the error occurring to less than one in every 10 15 clock cycles. if the MAX100 were operated at 250mhz, 24 hours a day, this would translate to less than one metastable-state error every 46 days. integral nonlinearity integral nonlinearity (inl) is the deviation of the transfer function from a reference line measured in fractions of 1lsb using a ?est straight line?determined by a least square curve fit. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured lsb step and an ideal lsb step size between adjacent code transitions. dnl is expressed in lsbs and is calculated using the following equation: [v meas - (v meas-1 )] - lsb dnl(lsb) = lsb where v meas-1 is the measured value of the previous code. a dnl specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. sampled data (t/h) t/h clk clk analog input t ad track t aj t aw track hold aperture delay (t ad ) aperture width (t aw ) aperture jitter (t aj ) figure 5. t/h aperture timing
MAX100 250msps, 8-bit adc with track/hold ______________________________________________________________________________________ 11 _______________detailed description converter operation the parallel or ?lash?architecture used by the MAX100 provides the fastest multibit conversion of all common integrated adc designs. the basic element of a flash (as with all other adc architectures) is the comparator, which has a positive input, a negative input, and an output. if the voltage at the positive input is higher than the negative input (connected to a reference), the out- put will be high. if the positive input voltage is lower than the reference, the output will be low. a typical n- bit flash consists of 2 n -1 comparators with negative inputs evenly spaced at 1lsb increments from the bot- tom to the top of the reference ladder. for n = 8, there will be 255 comparators. for any input voltage, all the comparators with negative inputs connected to the reference ladder below the input voltage will have outputs of 1, and all compara- tors with negative inputs above the input voltage will have outputs of 0. decode logic is provided to convert this information into a parallel n-bit digital word (the out- put) corresponding to the number of lsbs (minus 1) that the input voltage is above the level set at the bot- tom of the ladder. finally, the comparators contain latch circuitry and are clocked. this allows the comparators to function as described above when, for example, clock is low. when clock goes high (samples) the comparator will latch and hold its state until the clock goes low again. track/hold as with all adcs, if the input waveform is changing rapidly during the conversion the effective bits and snr will decrease. the MAX100 has an internal track/hold (t/h) that increases attainable effective-bits performance and allows more accurate capture of ana- log data at high conversion rates. the internal t/h circuit provides two important circuit functions for the MAX100: 1) its nominal voltage gain of 4 reduces the input dri- ving signal to ?70mv differential (assuming a ?.02v reference). 2) it provides a differential 50 input that allows easy interface to the MAX100. data flow the MAX100 contains an internal t/h amplifier that stores the analog input voltage for the adc to convert. the differential inputs ain+ and ain- are tracked con- tinuously between data samples. when a negative clk edge is applied, the t/h enters hold mode (figure 5). when clk goes low, the most recent sample is pre- sented to the adc? input comparators. internal pro- cessing of the sampled data is delayed for several clock cycles before it is available at outputs adata or bdata. all output data is timed with respect to dclk and dclk (figures 1?). __________applications information analog input ranges although the normal operating range is ?70mv, the MAX100 can be operated with up to ?00mv on each input with respect to ground. this extended input level includes the analog signal and any dc common-mode voltage. to obtain a full-scale digital output with differential input drive, a nominal +270mv must be applied between ain+ and ain-. that is, ain+ = +135mv and ain- = -135mv (with no dc offset). mid-scale digital output code occurs when there is no voltage difference across the analog inputs. zero-scale digital output code, with differential -270mv drive, occurs when ain+ = -135mv and ain- = +135mv. table 2 shows how the output of the converter stays at all ones (full scale) when over ranged or all zeros (zero scale) when under ranged. for single-ended operation: 1) apply a dc offset to one of the analog inputs, or leave one input open. (both ain+ and ain- are ter- minated internally with 50 to analog ground.) 2) drive the other input with a ?70mv + offset to obtain either full- or zero-scale digital output. if a dc common-mode offset is used, the total voltage swing allowed is ?00mv (analog signal plus offset with respect to ground). table 1. input voltage range **an offset v io , as specified in the dc electrical parameters, may be present at the input. compensate for this offset by either adjusting the reference voltage (va rt or va rb ), or introducing an offset voltage in one of the input terminals ain + or ain-. +135 -135 0 0 ain+** (mv) ain-** (mv) input 11111111 10000000 output code full scale mid scale msb to lsb -135 +135 +270 0 00000000 11111111 zero scale full scale 0 0 -270 0 10000000 00000000 mid scale zero scale single ended differential
MAX100 250msps, 8-bit adc with track/hold 12 ______________________________________________________________________________________ table 2. output mode control 0 x 0 0 x 1 mod a=b div 250 250 dclk* (mhz) data appears on adata only, bdata port inactive (figure 3). adata identical to bdata (figure 3). description 125 1 0 0 8:16 demultiplexer mode. adata and bdata ports are active. bdata carries older sample and adata carries most recent sam- ple (figure 4). 125 1 0 1 adata and bdata ports are active, both carry identi- cal sampled data. alternate samples are taken but dis- carded. 50 1 1 0 adata port updates data on 5th input clk. bdata port inac- tive. other 4 sam- pled data points are discarded. 50 1 1 1 adata and bdata ports are both active with identi- cal data. data is updated on out- put ports every 5th input clock (clk). the other 4 samples are discarded. r r r r parasitic resistance to comparators positive reference center tap negative reference r / 2 r / 2 va cts va ct va rbs va rb va rt va rts parasitic resistance figure 6. reference ladder string *input clocks (clk, c l k ) = 250mhz for all above combinations. in divide-by-2 or divide-by-5 mode the output clock dclk will always be a 50% duty-cycle signal. in divide-by-1 mode dclk will have the same duty cycle as clk. divide by 1 divide by 1 mode divide by 2 divide by 2 divide by 5 divide by 5
MAX100 250msps, 8-bit adc with track/hold ______________________________________________________________________________________ 13 reference the adc? reference resistor is a kelvin-sensed, center- tapped resistor string that sets the adc? lsb size and dynamic operating range. normally, the top and bottom of this string are driven with an op amp, and the center tap is left open. however, driving the center tap is an effective way to modify the output coding to provide a user-defined bilinear response. the buffer amplifier used to drive the top and bottom inputs will need to supply approximately 18ma due to the resistor string impedance of 116 mini- mum. a reference voltage of ?.02v is normally applied to inputs va rt and va rb . this reference voltage can be adjusted up to ?.4v to accommodate extended input requirements (accuracy specifications are guaranteed with ?.02v references). the reference input va rts , va rbs , and va cts allow kelvin sensing of the applied voltages to increase precision. an rc network at the adc? reference terminals is needed for best performance. this network consists of a 33 resistor connected in series with the op amp out- put that drives the reference. a 0.47? capacitor must be connected near the resistor at the op amp? output (see typical operating circuit ). this resistor and capacitor combination should be located within 0.5 inches of the MAX100 package. any noise on these pins will directly affect the code uncertainty and degrade the adc? effective-bits performance. clk and dclk all input and output clock signals are differential. the input clocks, clk and clk , are the primary timing sig- nals for the MAX100. clk and clk are fed to the inter- nal circuitry from pins 2 & 3 or pins 62 & 61 through an internal 50 transmission line. one pair of clk/clk inputs should be driven and the other pair terminated by 50 to -2v. either pair can be used as the driven inputs (input lines are balanced) for easy circuit con- nection. a minimum pulse width (t pwl ) is required for clk and clk (figures 1?). for best performance and consistent results, use a low phase-jitter clock source for clk and clk . phase jitter larger than 2ps from the input clock source reduces the converter? effective-bits performance and causes inconsistent results. dclk and dclk are output clock signals derived from the input clocks and are used for external timing of the adata and bdata outputs. the MAX100 is character- ized to work with maximum input clock frequencies of 250mhz (table 1). see typical operating circuit. output mode control div, mod, and a=b are input pins that determine the operating mode of the two output data paths. six options are available (table 1). a typical operating con- figuration (8:16 demultiplexer mode) is set by 1 on div, 0 on mod, and 0 on a=b. this will give the most recent sample at adata with the older data on bdata. both outputs are synchronous and are at half the input clock rate. to terminate the control inputs, use a resis- tor to -2v or the equivalent circuit resistor combination from dgnd to -5.2v up to 1k . when using a diode pull-up to tie an input high, bias the diode ?n?with a pull-down resistor to avoid input voltage excursions close to ground. the control inputs are compatible with standard ecl 10k logic levels over temperature. layout, grounding, and power supplies the MAX100 is designed with separate analog and dig- ital ground connections to isolate high-current digital noise spikes. the high-current digital ground, dgnd, is connected to the collectors of the output emitter fol- lower transistors. the low-current ground connection is gnd, which is a combination of the analog ground and the ground of the low-current digital decode section. the dgnd and gnd connections should be at the same dc level, and should be connected at only one location on the board. this will provide better noise immunity and highest device accuracy. a ground plane is recommended. a +5v ?% supply as well as a -5.2v ?% supply is needed for proper operation. bypass the vee and vcc supply pins to gnd with high-quality 0.1? and 0.001? ceramic capacitors located as close to the package as possible. an evaluation kit with a suggest- ed layout is available.
MAX100 250msps, 8-bit adc with track/hold 14 ______________________________________________________________________________________ MAX100 1/ 2 max412 1/ 2 max412 d > q q d > q q 8 d > q q d > q q 8 14 13 16 11 12 dclk dclk a=b div mod 1k 1k 1k 50 w 50 w 50 w -2v -2v -2v -2v clock bdata adata +5v 0.1 m f 0.001 m f 20 w 50 8, 21, 43, 56 51 55 72. 73 54 75, 76 2 62 3 61 ain+ ain- clk dgnd gnd sub vee 29 32, 69, 80 * -2v -2v clk *pins 68, 4, 7, 15, 49, 57, 60, 64 67, 70, 71, 74, 77, 78, 79, 82, 84, 18, 24, 27, 30, 34, 37, 40, 46 -5.2v 0.1 m f 0.001 m f 10 m f 0.47 m f va rt v cc va rts va rb va rbs 120 w 50 w 1.02v 0.01 m f 0.01 m f 2.5v mx580lh 1 3 2 +v s vout gnd 51 w 20k cmpsh-3 0.22 m f cmpsh-3 0.22 m f 51 w 20 w 33 w 20k 50k 70k 10k va ct va cts mc100e151 mc100e151 watkins-johnson smra 89-1 mc100e116 150 w 50 w ___________________________________________________typical operating circuit
MAX100 250msps, 8-bit adc with track/hold ______________________________________________________________________________________ 15 ____________________________________________________________pin configuration gnd clk clk n.c. 63 62 61 60 59 58 57 56 55 54 53 52 50 49 48 47 46 45 44 43 51 top view MAX100 vcc gnd n.c. n.c. va rbs va rb va rt va rts va cts va ct dgnd b0 n.c. gnd b1 a0 vcc gnd clk clk pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 vcc gnd n.c. n.c. n.c. n.c. dclk dclk mod div dgnd a7 a = b gnd a6 b7 vcc 84 83 82 81 80 79 78 77 n.c. gnd n.c. gnd gnd gnd gnd vee ain- ain- 74 75 76 69 70 71 72 73 68 67 66 65 gnd ain+ ain+ gnd gnd tp1 vee gnd tp3 tp2 64 gnd 24 25 26 27 28 29 b5 dgnd a5 b6 sub b4 dgnd a4 n.c. dgnd 34 35 33 32 31 30 39 38 37 36 n.c. dgnd n.c. vee a2 b3 dgnd a3 b2 dgnd 22 23 42 41 40 a1 ceramic flat pack
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1994 maxim integrated products printed usa is a registered trademark of maxim integrated products. MAX100 250msps, 8-bit adc with track/hold ________________________________________________________package information 0 100 200 300 400 500 7 MAX100-insertb velocity (ft /min) q ja (?/w) 12 11 13 15 17 19 21 23 pin fin heatsink forced convection parameters 45 degrees* *direction of airflow across heatsink 0 degrees* 0.060?005(7x) d3 0.075?020(6x) equal spaces d2 d d1 c pin #1 e s e2 e e1 b a2 a1 a 0.060?005 e3 5? 84 lead ceramic flat pack with heat sink millimeters inches a a1 a2 b c d d1 d2 d3 e e e1 e2 e3 s dim min max min max 17.272 1.041 3.048 0.406 0.228 29.184 44.196 25.298 28.448 29.184 44.196 25.298 28.194 1.930 18.288 1.270 3.302 0.508 0.279 29.794 44.704 25.502 28.829 29.794 44.704 25.502 28.702 2.184 0.680 0.041 0.120 0.016 0.009 1.149 1.740 0.996 1.120 1.149 1.740 0.996 1.110 0.076 0.720 0.050 0.130 0.020 0.011 1.173 1.760 1.004 1.135 1.173 1.760 1.004 1.130 0.086 1.270 bsc 0.050 bsc

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